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Digital Circuits And Design

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19k
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Design a circuit with optimum utilization of PLA to implement the following functions F1= $\sum m(0,2,5,8,9,11), F2=\sum m(1,3,8,10,13,15), F3=\sum m(0,1,5,7,9,12,14).$
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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17k
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Draw internal block diagram of IC 7490.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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16k
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Implement 10 bit comparator using IC 7485.
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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14k
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Use K-map to reduce following functions and then implement by NOR gates:
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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13k
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Simplify following logic function and realize using NOR gate:
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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11k
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Discuss XC 9500 CPLD family architecture with neat block diagram. Describe main features.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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10k
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Explain input and output block architecture for FPGA 4000 family.
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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10.0k
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Explain glitch problem of ripple counter along with waveform.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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9.9k
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Write a short note on : i) K-map
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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9.5k
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1
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Write short notes: SR flip flop
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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9.3k
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Short note on multiplexers.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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8.4k
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Draw truth table and logic diagram of Full Subtractor
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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7.8k
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**Implement following function using 8:1 MUX and logic gates.**
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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6.5k
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Write Short notes on: i) Noise margins
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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6.0k
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Draw and explain the block diagram of architecture of XC9500 CPLD family.
digital circuits and design updated 2.2 years ago by pedsangini276 • 4.8k
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5.9k
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Write short note on: JTAG and BIST
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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1
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5.8k
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1
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Explain current sinking and sourcing when two standard TTL gates are connected
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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5.8k
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1
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Explain Mealy and Moore sequential machine
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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4.7k
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Draw circuit diagram of 2 input TTL NAND gate
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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4.6k
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1
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Differentiate between Asynchronous and synchronous counters.
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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1
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3.9k
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1
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Eliminate redundant states and draw reduced state diagram
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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1
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3.9k
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1
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Design a Mealy type sequence detector to detect a serial input sequence of 101.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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3.8k
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Implement following function using 4:1 line MUX and NAND gates
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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1
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3.3k
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1
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Explain shift registers and its applications.
digital circuits and design updated 2.3 years ago by teamques10 ★ 65k
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3.2k
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1
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Write a VHDL code for full adder.
digital circuits and design updated 2.3 years ago by pedsangini276 • 4.8k
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